The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, is neither expressly nor impliedly admitted as prior art against the present disclosure.
Data error rates in traditional flash memory devices depend on the life-cycle of the memory. Specifically, the data integrity of the memory depends on a duration of time the data is retained in the memory as well as the number of program-erase (PE) cycles of the block, page or location where the data resides and many other factors. Traditional systems use error correction code circuitries (ECC) and encoding/decoding engines to detect/correct data errors encountered when writing/reading the data to/from the flash memory devices. Traditional systems may also remap blocks or storage locations to spread write operations across the device or mark blocks as bad to avoid future write operations to those blocks. Although these systems successfully address the flash memory data storage integrity, these methods oftentimes waste resources decoding and encoding data by using complex coding schemes when less complex coding schemes would suffice and therefore lack efficiency (i.e., wastes resources, consumes a large amount of power and increases decoding latency by taking more time to decode).